Article ID: 000074076 Content Type: Troubleshooting Last Reviewed: 04/02/2020

Do user I/O pins drive high during transition from input tri-state with weak pull-up to LVDS I/O standard in initialization stage in Stratix® V devices?

Environment

    Quartus® II Subscription Edition
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Description

Yes.  Due to the specifications of user I/O element, user I/O pins drive high during transition from input tri-state with weak pull-up to LVDS I/O standard in initialization stage in Stratix® V devices.  So the state of the user I/O pins designed as LVDS I/O standard change from weak pull-up to VCCIO, high state driven from VCCIO, to LVDS I/O standard in initialization stage.  

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Stratix® V FPGAs

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