Whatever turn on or turn off 100Ohm on chip input termination for LVDS IO in dedicated clock input pins of STRATIX 10 ES2 device, the test waveform will be the same as it is turned on. Turn-off input termination of LVDS by QSF or assignment editor cannot work actully.
The QSF settings are as below:
#To turn it off:
set_instance_assignment -name INPUT_TERMINATION OFF -to CLK_MPLL_FPGA_PL_REFCLK -entity termination_test
set_instance_assignment -name INPUT_TERMINATION OFF -to CLK_MPLL_FPGA_PS_REFCLK -entity termination_test
#To turn it on:
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CLK_MPLL_FPGA_PL_REFCLK -entity termination_test
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CLK_MPLL_FPGA_PS_REFCLK -entity termination_test
It is identified that software is always setting Rd_termination to ON regardless of the direction of the buffer. It is more reasonable that Rd_termination could be turned ON and OFF when LVDS I/O standard is used for input signal.
We will fix it in Quartus prime® version 18.1.
And for Quartus prime® version 17.1.2 and 18.0, patch will be provided for solving this issue.