Due to a problem in the Intel® Quartus® Prime Pro Edition software version 18.1.1 and early, there are 6 RS-FEC blocks in the Intel® Stratix®10 FPGA E-tile device family, and each RS-FEC block share 4 channels. There are 6 channels in total (1 channel per RS-FEC block) in the E-tile which are used to handle AVMM2 RS-FEC data. These channels are 3, 7, 11, 15, 19 and 23. If any of these channels are instantiated in non-FEC mode in an IP, and the other channels within the same RS-FEC block are instantiated with RS-FEC in a separate IP, this will cause a fitter error.
Currently there is no workaround for this problem. This problem is schedule to be fixed on a future Intel® Quartus® release.