Article ID: 000073944 Content Type: Troubleshooting Last Reviewed: 03/15/2021

Why does FPGA configuration fail from HPS on Intel® Stratix® 10 SX devices when I configure phase 2 bitstreams in HPS boot first mode?


  • Intel® Quartus® Prime Pro Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition

    Critical Issue


    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3, phase 2 bitstream core.rbf configuration from HPS as part of an HPS boot first mode may fail for designs targeting Intel Stratix® 10 SX devices.

    The following errors may be seen:

     fpga_manager fpga0: Error while writing image data to FPGA
     failed to load fpga image
    OF: overlay: of_overlay_create: Pre-apply notifier failed (err=-110)
    create_overlay: Failed to create overlay (err=-110)


    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 19.3. Download and install Patch 0.48fw from the appropriate link below.

    You must install the Intel® Quartus® Prime Pro Edition software version 19.3 software before installing this patch:  

     Download patch quartus-19.3-0.48fw for Windows (.exe)

     Download patch quartus-19.3-0.48fw for Linux (.run)

     Download the Readme for patch 19.3-0.48fw (.txt)

    This problem is fixed in the Intel® Quartus® Prime Pro software version 20.2 and onwards.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA



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