Article ID: 000073880 Content Type: Troubleshooting Last Reviewed: 06/06/2019

What is the RGMII TX_CLK clock period timing tolerance in Arria® V Device Datasheet?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Arria® V Device Datasheet, the Min/Max value for the TX_CLK period is not provided in the Ethernet Media Access Controller (EMAC) timing characteristics table in the HPS specifications section. 

Resolution

Tclk Min/Max specifications are below as reference.

Symbol

Description

Min

Typ

Max

Unit

Tclk(1000Base-T)

TX_CLK clock period

7.2

8.0

8.8

ns

This problem is scheduled to be fixed in a future release of the Cyclone® V/Arria® V Device Datasheet.

Related Products

This article applies to 2 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA

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