Article ID: 000073867 Content Type: Troubleshooting Last Reviewed: 03/07/2023

Why do Intel Agilex® 7 devices not configure successfully during power up but can then be reconfigured successfully?


  • Intel® Quartus® Prime Pro Edition

    When using Intel Agilex® 7 devices, you may observe a glitch on PWRMGT_SCL and PWRMGT_SDA pins during device power-up. Depending on your board design and power regulator, the glitch may trigger a NACK condition to the Intel Agilex® 7 device or voltage regulator, which will cause the Intel Agilex® 7 device to fail configuration.

    When this occurs, you will  see the following SDM status when captured according to AN 936: Executing SDM Commands via JTAG Interface:

        State: 0xf0020032
        Error location : 0x00001800
        Error detail : 0x00200008

        Configuration fail!
        Major code: 0xF002
        Fail to access QSPI or PMBus voltage regulator (VID).

        Minor code: 0x0032
        PMF initialization error, check your PMBus connection between SDM_IO and power regulator.

    Subsequent reconfiguration without a power cycle is successful. 


    Note that the PWRMGT_SCL and PWRMGT_SDA signals are in an undetermined state during device power-up and power-down. It is therefore recommended to hold voltage level translators (used for the PMBus interface between the FPGA and voltage regulator) disabled by default to ensure that bus contention, excessive currents, or oscillations do not occur during FPGA power supply rail ramp-up and power down.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs