The Quartus® II software reports the lock range of any PLL used in the design in the Compilation Report - Fitter - Resource Usage - PLL Summary. The range between the Freq min lock and Freq max lock is referred to as the lock range of the PLL. The Quartus II software does not select PLL parameter values to maximize the lock range.
For example, if you used 75MHz as the input clock in the PLL MegaWizard® Plug-In Manager, the lock range may be 70MHz to 90MHz. Perhaps in your application you would require a lock range anywhere between 50MHz and 100MHz. Thus, the lock range of this PLL would not be satisfactory for your application.
You can use the PLL MegaWizard Plug-In Manager in the Quartus II software to help maximize your lock range for devices that support the input clock switchover feature. The intention of this solution is to not use clock switchover in the final design, but to use the feature to extract valid parameter values for the PLL to maximize the lock range by following these steps:
1) Open the PLL MegaWizard Plug-In Manager.
2) Enter the frequency you desire for the low end of your lock range in the "What is the frequency of your inclock0 input?". For example given above, this value would be 50MHz.
3) Turn on the option to "Create output file(s) using the 'Advanced' PLL parameters" option.
4) Turn on the option to "Create an 'inclk1' for a second inclk" and enter the high end of your lock range as the frequency for inclk1. For example given above, this value would be 100MHz.
5) Complete the PLL wizard as you normally would with the rest of your options selected and output clock ratios defined.
6) Compile your project and note the lock range as shown in the PLL summary. If it is satisfactory, note all of the values for the PLL from this report such as the M value, N value, Charge pump current, Loop filter resistance, and Loop filter capacitance from the PLL summary report. Also note the high/low and even or odd values for each output clock as shown in the PLL Usage report.
7) Open the PLL wizard and turn off the option to "Create an 'inclk1' for a second inclk". Click "Finish" to update the PLL wrapper file.
8) Open the PLL wrapper file. When using advanced parameters, you can directly enter the PLL parameters into the code. If the wrapper file is Verilog, go to the defparam section. If the wrapper file is VHDL, go to the generic map section. Modify all of the values for the parameters listed in step 6. Save the changes.
9) Compile your project. The end result should be a PLL with the lock range you desire.
10) If the lock range is too close to your input frequency, for example, the low end is 50MHz and you intend on using a 50MHz input clock, you may have difficulties with the PLL maintaining lock if the input clock has jitter or any frequency drift below 50MHz. You may decide to give a little guardband to your inclock0 and inclock1 frequencies in the wizard. For this example, you could enter 45MHz and 105MHz so your target lock range of 50MHz to 100MHz is well within the PLL lock range.
If the Quartus II software can not implement your desired lock range using this procedure, you will receive an error in the PLL MegaWizard Plug-In Manager. In that case, you will have to look into other options such as PLL reconfiguration in order to support your required input clock frequency range.