You might see this warning in the Quartus® II software design fitter report if a phase locked loop (PLL) that has the reconfiguration option enabled does not have a compensated clock specified.
To set the PLL compensation targets for the PLL Intel® FPGA IP for reconfigurable PLLs, create a “Match PLL Compensation Clock” assignment in the Quartus II Assignment Editor.
The syntax of the PLL clock node has to be specific for it to be saved in the Assignment Editor. Filter on *divclk[* in a post compilation filter in the node finder to find the correct name.
For example:
clkrst:u_clkrst|adc_pll_ip:u_adc_pll_ip|adc_pll_ip_0002:adc_pll_ip_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]
Where divclk[0] corresponds to Counter CO in this PLL Intel® FPGA IP instance.
This workaround/fix is for PLLs that have the reconfiguration feature enabled. See the related solution for PLLs without the reconfiguration feature enabled.