Where is the Cache-Coherence Protocol Directory Placed in Intel® Xeon® Processors?

Seeking detailed information on the cache-coherence protocol for Intel® Xeon® Processors, specifically regarding the location of the directory within the architecture, with particular emphasis on Non-Uniform Memory Access (NUMA) configurations.

The cache-coherence protocol integrated into Intel® Xeon® Processors is a fundamental feature of the Intel® Ultra Path Interconnect (Intel® UPI) system utilized by these processors. This protocol is essential for maintaining data consistency, governing how caching agents must operate, and facilitating coherent memory read and write processes to ensure efficient interaction between the processor and memory.

Using this directory information, the home agent can pinpoint the minimal necessary snoops needed and decide when to dispatch data and completion to a request before receiving all the snoop responses. Directory states can convey whether all caches associated with the directory hold a particular state, specify states in the caches owned by coherence agents, or indicate any potential state of the line across caches.

In multi-processor systems, the directory facilitates cache coherence by functioning as a distributed in-memory directory. Here, the coherence state of each cache line is stored as metadata within the memory line, advancing beyond pure snoop-based systems that necessitate processors to consistently verify other processors’ caches for coherence state, thus reducing access latency.

As specified in the Intel® 64 and IA-32 Architectures Optimization Reference Manual Volume 1, the cache-coherence protocols effectively manage instances where multiple processors cache identical memory locations during atomic operations.

IA-32 Architecture Compatibility: When a LOCK prefix is applied to an instruction with memory cached internally, the LOCK# signal is generally not invoked. Instead, the processor locks its cache, utilizing the cache-coherence mechanism to ensure atomic execution concerning memory access. More information on cache locking is available in the section "Effects of a Locked Operation on Internal Processor Caches" found in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4.

Regarding Coherence Overhead Measurement: Intel has not designated a specific tool for measuring coherence overhead. This assessment would involve calculating the requisite bits for the cache and dividing by the cache size, or a similar method.