Intel® Xeon® Scalable processors are typically single-chip modules. Each processor is a single piece of silicon, also known as a monolithic die, that contains all the cores, cache, memory controllers, and other features. This has traditionally been the case for most server-grade CPUs, including those in the Xeon Scalable family.
However, with advancements in technology and increasing core counts, Intel and other CPU manufacturers have explored and developed multi-chip module (MCM) designs. MCMs allow for a processor to be composed of several small dies, or chipsets, that are interconnected within a single package. This can improve yields, reduce costs, and allow for more scalable designs.
The 4th Gen Intel® Xeon® Scalable Processors (formerly codenamed Sapphire Rapids) and the 5th Generation Intel® Xeon® Scalable Processors (formerly codenamed Emerald Rapids) utilize different architectures.
For example, the 4th Gen Intel® Xeon® Scalable Processors based on the Sapphire Rapids architecture utilize a multi-tile (multi-chip) approach. This is part of Intel's strategy to keep up with the core count and performance demands of modern data centers and high-performance computing applications.
The 5th Gen Intel® Xeon® Scalable Processors are single-die package processors for Medium Core Count (MCC) and Low Core Count (LCC) SKUs, or multi-chip modules for Extreme Core Count (XCC) SKUs.
This single-die construction enhances the overall product yield and is constructed as a single monolithic chip with a full mesh architecture, allowing up to 32 active cores. For the multi-tile (multi-chip) approach, the modules are connected by an Embedded multi-die interconnect bridge (EMIB).
It's important to note that the specifications can change with each new generation of processors, so for the most up-to-date information, you should refer to the latest Intel® Product Specifications.