Jump Conditional Code Erratum Overview White Paper for Intel® Processors


Product Information & Documentation



Starting with the second-generation Intel® Core™ Processors and Intel® Xeon® E3-1200 Series Processors (formerly codenamed Sandy Bridge) and later processor families, the Intel® microarchitecture introduces a microarchitectural structure called the Decoded ICache (also called the Decoded Streaming Buffer or DSB).

The Decoded ICache caches decoded instructions, called micro-ops (μops), coming out of the legacy decode pipeline. The next time the processor accesses the same code, the Decoded ICache provides the μops directly, speeding up program execution.

In some Intel® Processors, there's an erratum (SKX102) that may occur under complex microarchitectural conditions involving jump instructions that span across 64-byte boundaries (cross cache lines).  A microcode update (MCU) can prevent this erratum.

For more information about this erratum including how to get the MCU and a list of processor families/processors number series, view the Mitigations for Jump Conditional Code Erratum White Paper (attached below).

  • Not all product names/SKUs under a series are affected.  For example, not all SKUs under Intel® Core™ X-series Processors are affected.  Please refer to the “Affected Processors” section of the attached PDF.
  • If the GitHub* link doesn't have the information needed for your system, contact your system manufacturer for the most recent update.

Mitigations for Jump Conditional Code Erratum White Paper (PDF) PDF icon

Size: 362 KB
Date: November 2019

Note: PDF files require Adobe Acrobat Reader*.