Technologies Defined for Intel® Mobile and Desktop Processors

Intel® Turbo Boost Technology is one of the many exciting new features that Intel has built into latest-generation Intel microarchitecture. It automatically allows processor cores to run faster than the base operating frequency if it's operating below power, current, and temperature specification limits.

The maximum frequency of Intel Turbo Boost Technology is dependent on the number of active cores. The amount of time the processor spends in the Intel Turbo Boost Technology state depends on the workload and operating environment, providing the performance you need, when and where you need it.

Any of the following can set the upper limit of Intel Turbo Boost Technology on a given workload:

• Number of active cores
• Estimated current consumption
• Estimated power consumption
• Processor temperature

When the processor is operating below these limits and the user's workload demands additional performance, the processor frequency will dynamically increase by 133 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached.

Intel® AES instructions are a new set of instructions available beginning with the 2010 Intel® Core™ Processor Family based on the 32nm Intel® microarchitecture. These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (AES), which is defined by FIPS Publication number 197. Since AES is currently the dominant block cipher, it is used in various protocols. The new instructions are valuable for a wide range of applications.

The architecture consists of six instructions that offer full hardware support for AES. Four instructions support the AES encryption and decryption, and the other two instructions support the AES key expansion.

The AES instructions have the flexibility to support all usages of AES, including all standard key lengths, standard modes of operation, and even some nonstandard or future variants. They offer a significant increase in performance compared to the current pure-software implementations.

Beyond improving performance, the AES instructions provide important security benefits. By running in data-independent time and not using tables, they help in eliminating the major timing and cache-based attacks that threaten table-based software implementations of AES. In addition, they make AES simple to implement, with reduced code size, which helps reducing the risk of inadvertent introduction of security flaws, such as difficult-to-detect side channel leaks.

Intel® 64 Architecture is an enhancement to the Intel IA-32 architecture. The enhancement allows the processor to run 64-bit code and access larger amounts of memory.

Intel 64 Architecture delivers 64-bit computing on server, workstation, desktop and mobile platforms when combined with supporting software. Intel 64 Architecture improves performance by allowing systems to address more than 4 GB of both virtual and physical memory.

Intel 64 provides support for the following:

• 64-bit flat virtual address space
• 64-bit pointers
• 64-bit wide general purpose registers
• 64-bit integer support
• Up to one terabyte (TB) of platform address space

A C-state is an idle state. Modern processors have several different C-states representing increasing amounts of pieces to shut down. C0 is the operational state, meaning that the CPU is doing useful work. C1 is the first idle state. The clock running to the processor is gated. In other words, the clock is prevented from reaching the core, effectively shutting it down in an operational sense. C2 is the second idle state. The external I/O Controller Hub blocks interrupts to the processor. And so on with C3, C4, etc.

A core C-state is a hardware C-state. There are several core idle states, like CC1 and CC3. As we know, a modern state-of-the-art processor has multiple cores. What we used to think of as a CPU or processor actually has multiple general purpose CPUs inside of it. The Intel® Core™ Duo Processor has two cores in the processor chip. The Intel® Core™2 Quad Processor has four such cores per processor chip. Each of these cores has its own idle state. This makes sense as one core might be idle while another is hard at work on a thread. So, a core C-state is the idle state of one of those cores.

A processor C-state is related to a core C-state. At some point, cores share resources, like the L2 cache or the clock generators. When one idle core, say core 0, is ready to enter CC3 but the other, say core 1, is still in C0, we do not want the fact that core 0 is ready to descend into CC3 to prevent core 1 from executing because we just happened to shut down the clock generators. Thus we have the processor or package C-state, or PC-state. The processor can only enter a PC-state, say PC3, if both cores are ready to enter that CC-state, e.g. both cores are ready to step into CC3.

A logical C-state: The last C-state is the OS's view of the processors' C-states. In Windows, a processor's C-state is pretty much equivalent to a core C-state. In fact, the OS's lower level power management software determines when and if a given core enters a given CC-state using the MWAIT instruction. There is one important difference. When an application, such as Intel® Power Informer, thinks it's interrogating a processor core CC-state, what is returned is the C-state of what is called a logical core. A logical core is technically not the same as a physical core. Logical cores don't have to worry about little things such as the hardware the OS is running on. For example, the C-state of a logical core doesn't worry about the barriers imposed by shared resources, such as the clock generators discussed earlier. Logical Core 0 can be in C3 while Logical Core 1 is in C0.

For a deeper explanation of C states, please refer to the following article: (update) C-states, C-states and even more C-states.

Enhanced Intel SpeedStep® Technology is an advanced technology which significantly reduces the processor voltage (and temperature), hence leakage power, when processor activity is low. Enhanced Intel Speedstep Technology has revolutionized thermal and power management by giving application software greater control over the processor's operating frequency and input voltage. Systems can easily manage power consumption dynamically.

Separation between Voltage and Frequency Changes
By stepping voltage up and down in small increments separately from frequency changes, the processor is able to reduce periods of system unavailability (which occur during frequency change). Thus, the system is able to transition between voltage and frequency states more often, providing improved power/performance balance.

Clock Partitioning and Recovery
The bus clock continues running during state transition, even when the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core clock is also able to restart far more quickly under Enhanced Intel SpeedStep Technology than under previous architectures.

Operation of a processor above the manufacturer’s specified frequency (e.g. operating at 3.2 GHz with a processor that Intel manufactured to run at 2.8 GHz).

A processor being operated above its frequency specification (overclocked) may become unstable, or produce unpredictable or erroneous results. These conditions might not be readily apparent, and the life of the processor may also be shortened. Intel’s warranty does not cover processors that have been overclocked.

The Micro-FCBGA (FCBGA rBGA or BGA) and The Micro-FCPGA (FCPGA, rPGA, PGA)

The Micro-FCBGA (Flip Chip Ball Grid Array) is Intel's current BGA mounting method for mobile processors that use a flip chip binding technology. It was introduced with the Mobile Intel® Celeron® Processor. This is thinner than a pin grid array socket arrangement, but is not removable (solider to the board).

A flip chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have more direct contact with the heatsink or other cooling mechanism.

The FC-PGA was introduced by Intel with the Intel® Pentium® III and Celeron® Processors based on Socket 370, and was later used for Socket 478-based Intel® Pentium® 4 and Celeron® Processors. FC-PGA processors fit into zero insertion force (ZIF) Socket.

• uPGA/BGA - a Micro Pin Grid Array or Ball Grid Array package.
• OOI - an OLGA (Organic Land Grid Array) On Interposer package translates the fine pitch pads of the OLGA package to a pin field, which connects into the socket on the system main board.
• uFCPGA or uFCPGA2 - a Micro Flip Chip Pin Grid Array package.
• uFCBGA or uFCBGA2 - a Micro Flip Chip Ball Grid Array package.
• FCPGA(Pin Count) 946/946B, uses a Socket G3/rPGA946B/rPGA947.
• FCBGA(Pin Count) 1168/1364, BGA does not use a socket, directly connected to the board.
• LGA1366 - a 1366 pin Land Grid Array package.
• LGA1156 - a 1156 pin Land Grid Array package.
• LGA775 - a 775 pin Land Grid Array package.
• LGA771 - a 771 pin Land Grid Array package.

For more information, see the Intel® Desktop Processors package type guide.

This classification indicates the Intel® Microprocessor generation and brand. For example, Intel® Pentium® 4 Processors have a Family value of F.

This information can be useful for validating information from the Quick Reference Guide available for the specific family of your processor.

• Type 1 indicates that the microprocessor was intended for installation by a consumer (for example, upgrade such as an Intel® OverDrive® Processor).
• Type 0 indicates that the microprocessor was intended for installation by a professional PC system integrator, service company or manufacturer.