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Potential for signature integrity compromise in Intel® Integrated Performance Primitives (Intel® IPP) Cryptography Domain
The cryptography (CP) domain in Intel’s newest version of Intel® Integrated Performance Primitives (Intel® IPP) v7.1 has been enhanced to improve its security and customers are strongly urged to update to this release.
Intel IPP v7.1 introduces Intel® AVX & Intel® AVX2 performance optimizations for faster floating-point and integer operations in the signal processing and image processing domains. Additional Improvements have been made to the CP domain including AES key expansion, RSA-based signature generation and ECC prime field point multiplication. Customers can get these security improvements by linking with v7.1 of Intel® IPP. For additional information on performance impact to RSA and ECC functions, please see the Recommendations below.
The cryptography (CP) domain in Intel® Integrated Performance Primitives (Intel® IPP) versions prior to 7.1.
Customers are strongly urged to update to version 7.1 which can be obtained from this URL: http://software.intel.com/en-us/articles/download-ipp-cryptography-libraries/
To mitigate the potential reduction in performance, some source code changes are recommended for RSA functions. The following RSA functions can be can be initialized two different ways:
- private key pair:
- ippsRSASetKey(pD, ippRSAkeyD, pRSA)
- ippsRSASetKey(pN, ippRSAkeyN, pRSA)
- private key quintuple:
- ippsRSASetKey(pP, ippRSAkeyP, pRSA)
- ippsRSASetKey(pQ, ippRSAkeyQ, pRSA)
- ippsRSASetKey(pdP, ippRSAkeyDpP, pRSA)
- ippsRSASetKey(pdQ, ippRSAkeyDq, pRSA)
- ippsRSASetKey(pQinv, ippRSAkeyQinv, pRSA)
If a private key quintuple is used, code changes should be made to additionally provide the private exponent by the calling ippsRSASetKey(pE, ippRSAkeyE, pRSA) function to avoid a 3-4x performance penalty to RSA Sign operations.
Finally for ECC functions some performance degradation, perhaps up to 10%, may be expected for the functions:
At this time there is no known mitigation for this performance impact in ECC.
Optimization Notice Notice revision #20110804
Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
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