Intel Labs Establishes Resilient Architectures and Robust Electronics Multi-University Research Center


  • Resilient Architectures and Robust Electronics (RARE) research center focuses on developing new capabilities for secure and resilient hardware and software.

  • Research areas include error characteristics of silicon computing, new solutions to detect compute failure conditions, tools for side-channel-free and fault-tolerant processors, and novel hardware mitigations.

  • Researchers from the following leading universities were selected to participate in the research center: University of California San Diego, Columbia University, Georgia Institute of Technology, Graz University of Technology, University of Illinois, Massachusetts Institute of Technology, University of Minnesota, Purdue University, University of Texas at Austin, and University of Washington.



Intel Labs' University Research & Collaboration Office (URC) is pleased to announce the opening of a new multi-university research center called Resilient Architectures and Robust Electronics (RARE). The center will focus on assessing and improving the resiliency, reliability, and security of Intel® hardware and software, including the security of Intel® silicon integrated circuits. In addition, all research will be made public to the general semiconductor industry.

Academic researchers from 10 leading universities were selected to develop new capabilities to help increase the reliability and security of computing technologies. Research areas include systematic mitigation of error conditions and faults and associated impacts on future CPU architectures and implementations. These include faults caused by natural radiation, aging, random effects, noisy environments, and electronic glitches. In addition, research will also investigate intentionally caused faults such as fault injection attacks.

"Securing Intel technology and increasing the reliability of our semiconductors is our top priority," said Frank McKeen, senior principal engineer, Intel Labs. "Environmental anomalies and fault injection attacks, for example, are becoming more common, and there is a need to increase error detection and discover new ways to recover from errors. Through collaborating with these leading academic researchers, we will find solutions and novel approaches to these important industry-wide electronic security challenges."

The center launched in Q4 of 2021 and will operate for three years. The main research areas include:

Error characteristics of computing: Identify silicon failure mechanisms that result in computer errors of various types and provide mitigations of and response to these conditions.

  • New solutions, techniques, and mechanisms to detect compute failure conditions: Improve the handling of compute failures by providing new detection and mitigation mechanisms.
  • Research and tools for side-channel-free and fault-tolerant processors: Advance research related to speculative execution and other security issues such as fault injection attacks.
  • Novel hardware mitigations: Advance secure, confidential computing with new concepts learned from a clean slate processor design. 

Following is a list of participating universities and their specific areas of research:

  • Security Extensions with Speculatively Safe Formal Guarantees
    Deian Stefan, University of California San Diego

    Professor Stefan's team aims to improve the security of very large software systems like Firefox and Chrome. The research will tackle memory safety and Spectre attacks using a verified hardware/software co-design approach. The team will analyze and repurpose existing hardware extensions and design new (verified) extensions to help developers efficiently enforce speculative memory safety and speculatively safe in-process isolation.
  • SHEAR: Software and Hardware for Error and Attack Detection and Reasoning in a Microprocessor
    Mingoo Seok, Columbia University

    This project aims to create hardware and software techniques that can give a microprocessor the capability to detect and infer the causes of errors and attacks to improve the robustness, reliability, and security of a microprocessor. Specifically, we will pursue the following three sub-tasks: error/low-margin detection circuits that are designed for non-core blocks such as a network-on-chip; integrated power management hardware that can detect a side-channel attack (SCA) attempt and enable protection schemes only if it detects an SCA attempt; hardware and software interface and an inference model that leverages the hardware developed above to infer the causes of errors.
  • Protecting SoCs Against Laser Attacks
    Arijit Raychowdhury, Georgia Institute of Technology

    Professor Raychowdhury's team aims to protect system-on-a-chip (SoC) circuits against laser-based localized optical fault injection attacks by providing a first layer of passive defense and combining it with actively sensing an ongoing attack while incurring low hardware overheads. As a passive countermeasure, this research project will investigate the feasibility of using diffraction gratings (formed at the top metal layers on the front side of silicon or buried power lines on the backside) to defocus and effectively block commonly used collimated laser beam wavelengths for such attacks.

    On the other hand, to provide active protection, the research will explore the use of Mott device-based sensors tuned for specific intensity that is much lower than peak laser intensity. This involves using circuit design techniques and strategic placement of such sensors to minimize area overhead while protecting specific blocks of interest, such as encryption/decryption engines.
  • Unified Hardware Extensions for Better Architectural and Microarchitectural Isolation
    Stegan Mangard, Graz University of Technology
    Daniel Gruss, Graz University of Technology

    The Graz University of Technology team will work on novel isolation mechanisms in hardware to increase platform security in modern cloud scenarios. The research aims to create unified and highly flexible architectural mechanisms for sandboxes and enclaves at different levels of granularity. A particular focus is on mechanisms for achieving efficient fine-grained isolation. At the same time, the goal is also to create efficient mechanisms to prevent side-channel attacks and ensure isolation at the architectural and microarchitectural levels.
  • Usable, Performant Enclaves in Multicore Processor
    Srini Devadas, Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory

    The Spectre and Meltdown attacks caught the computer-security community off-guard, showcasing surprising opportunities for information leaks through timing-side-channels, thus defeating conventional process isolation. One promising way forward is using secure enclave systems designed to close all timing-side-channels. However, as is typical with security, a practical solution must clear the bar in several dimensions.

    Performance must be sufficient through compatibility with the latest techniques for multicore speculative execution. Usability challenges have slowed adoption of commercial systems with less-stringent isolation. We propose developing an open-source, RISC-V-based enclave system that brings together these two elements. Our research will study the combination of a timing-side-channel-proof enclave system with primitives for enclave-to-enclave communication on multicore speculative processors to enable irregular communication that is secure yet performant.​
  • On-Chip Telemetry for Tracking Compute Failures
    Chris Kim, University of Minnesota

    ​Leveraging their experience of designing compact on-chip aging sensors, Professor Kim's team will develop synthesizable "odometer" circuits amenable to being deployed in high-volume microprocessor products. Additionally, the team will design a CPU testbed with specialized built-in self-test circuits for characterizing compute failures under various stress conditions and security attacks. The unique test data from the odometers and CPU testbed will be used to understand the true nature of compute failures occurring in high-performance microprocessors.
  • Understanding in the Photonic Side-Channel: White-Box Model and Low-Overhead Generic Defenses
    Shreyas Sen, Purdue University

    The Purdue SparcLab team is focused on developing an in-depth theoretical understanding of advanced physical side-channel leakage mechanisms from cryptographic integrated circuits, i.e., going from a black-box to a physics-driven white-box model of leakage. Such deep knowledge then allows the development of new techniques of stopping the leakage at the source itself, using physical-, circuit-, or system-level techniques with the lowest overhead possible. This project aims to explore the fundamentals of a photonic side-channel among other advanced physical side-channels.
  • Scaling Processors to Hundreds of Security Domains
    Mohit Tiwari, University of Texas at Austin
    Christopher Fletcher, University of Illinois at Urbana-Champaign
    Josep Torrellas, University of Illinois at Urbana-Champaign

    Applications such as data-analytics pipelines, browsers, and service meshes operate on hundreds of concurrent security domains on each machine. Current approaches to isolating security domains rely primarily on strict partitioning of state and lose both performance and measurable guarantees in such over-committed environments. This project proposes many-domain architectures - from programming models down to micro-architecture - to securely multiplex hundreds of concurrent security domains in modern applications.
  • Exploring Formal Optimization and Robust Control for Secure Power Delivery Systems
    Visvesh Sathe, University of Washington 
    Baosen Zhang, University of Washington

    Integrated systems rely on increasingly complex voltage regulation (VR) architectures and control laws to provide fine-grained voltage control with rapid transient response to disturbances for energy-efficient operation. These trends have significantly degraded the designer's ability to identify, and therefore design for, worst-case operating conditions, leading to a harsh security-efficiency tradeoff. This effort involves leveraging formal optimization methods for designing optimal "load-viruses" that identify worst-case conditions at design time and can eventually be used to implement more effective VR architectures and control laws.