Intel and Intel Labs Present 14 Papers at ISSCC 2021

Researchers from Intel and Intel Labs will present 14 papers at the virtual 2021 IEEE International Solid-State Circuits Conference (ISSCC) on February 13-22. The conference showcases advances in solid-state circuits and systems-on-a-chip. Intel Labs will present research on quantum computing, silicon photonics, DC-DC converters, and other cutting-edge research on integrated circuit design and application. Intel also was recognized with an Outstanding Evening Session Award for a session presented at last year’s conference.

Papers will be available to members at the IEEE Xplore website.

Intel Labs Papers at ISSCC 2021

Spin qubits with an integrated cryo-CMOS controller represent a very promising architecture to enable scalable fault-tolerant quantum computers, according to “A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology” by J-S. Park, S. Subramanian, L. Lampert, T. Mladenov, I. Klotchkov, D. J. Kurian, E. Juarez-Hernandez, B. Perez-Esparza, S. R. Kale, A. B. K. T., S. Premaratne, T. Watson, S. Suzuki, M. Rahman, J. B. Timbadiya, S. Soni, and S. Pellerano. Researchers demonstrated a fully-integrated cryo-CMOS SoC capable of state manipulation, readout, and gate pulsing of spin qubits, in 22nm FinFET technology. The SoC integrates a micro-controller core and operates at 4K in the refrigerator. It can drive up to 16 qubits, perform concurrent readout on up to 6 SETs, and pulse up to 22 gates simultaneously. This research contributed to the introduction of Intel's second generation cryogenic quantum control chip, Horse Ridge II.

In the paper, “A 100Gb/s -8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS,” researchers H. Li, J. Sharma, C-M. Hsu, G. Balamurugan, and J. Jaussi presented a 100G PAM4 optical RX with a single-chip solution integrating all the RX electronics in a bulk CMOS process. Optical RX sensitivity measurements at 100 Gb/s PAM4 was -8.2 dBm. Measured power dissipation of the RX electronics was 390 mW at 100 Gb/s PAM4, resulting in 3.9 pJ/bit efficiency. This research is helping to pave the way for the extended use of silicon photonics beyond the upper layers of the network to inside the server and onto future server packages.

Ganging multiple tiles of IVRs with voltage-mode control (VMC) can result in unequal currents across tiles, impacting efficiency and reliability, according to “Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing” by N. Desai, H. K. Krishnamurthy, K. Ahmed, S. Weng, S. Kim, X. Liu, H. T. Do, K. Radhakrishnan, K. Ravichandran, J. W. Tschanz, and V. De. Researchers presented a 60MHz, ganged IVR with peak current-mode control (CMC) using 2-5.5nH ACI/SMD inductors. One-cycle response of the CMC was demonstrated with 1.2% current sharing accuracy across 2 tiles in a ganged IVR scenario. The CMC’s sharing accuracy across asymmetric loading, PDN and reference mismatch has been contrasted with the VMC.

Intel and Research Partner Papers at ISSCC 2021

Ultra-High-Speed Wireline

  • A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

ML Processors from Cloud to Edge

  • A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Continuous-Time ADCs and DACs

  • A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET
  • A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters

Advanced Wireline Links and Techniques

  • A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET
  • A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler

Computation in Memory

  • eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

Digital Circuits for Computing, Clocking, and Power Management

  • 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self-Referenced Asynchronous Adaptive Droop Mitigation

Non-Volatile Memory

  • A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density

Frequency Synthesizers

  • A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

Hardware Security

  • An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control

Award for ISSCC 2020 Session

During ISSCC 2021, two Intel researchers, Mondira Pant and Farhana Sheikh, were part of the team that was recognized with an Outstanding Evening Session Award for a well-received session presented at last year’s conference. At ISSCC 2020, this team of industry and academic circuit field experts organized the tongue-in-cheek event “Quiz Show: The Smartest Designer in the Universe.” Three teams representing academia, industry, and students competed in five rounds of serious and not-so-serious questions for the prestigious title of “the smartest designer in the universe.” Teams received help from the audience via smartphone to answer questions on history and the future of microelectronics.