Course DescriptionThis presentation describes good practices for designing high-speed core logic in Intel® FPGAs. As bandwidth rises and time to market pressures increase, it’s more critical to always use good design practices to ensure a quick design and timing closure cycle. These techniques are useful even if your design runs at slower speeds since they still can make it easier for you to close timing, regardless of the target clock frequency of the design. These techniques can also provide the benefit of shorter compile times.
At Course Completion
You will be able to:
- Understand the mindset you should have as a designer to get the best results
- Employ pipelining
- Reduce logic depth
- Understand tradeoffs with bus width and speed
- Be aware of how physical implementation affects performance
- Manage high fanout
- Employ flow control techniques.
- An understanding of basic FPGA design flow
- Familiarity with VHDL or Verilog HDL
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: