Are you beginning or working on a design that uses one or more PCI Express® interfaces? Do you have questions regarding bringing up your FPGA’s PCIe® link? Then this course should be of interest to you!
We'll start with a high-level overview of the PCI Express protocol and from there you'll learn the design flow to target the Hard IP for PCI Express blocks found in Cyclone® V, Arria® V, Stratix® V and Arria 10 devices, particularly when using the Qsys system design tool. You'll see how to debug and test your PCIe links, both through simulation and in-system. You'll discover advanced device features to add more flexibility and capability to your PCI Express-based design. By the end of the day, you'll feel comfortable getting your own device’s PCIe link up and running.
At Course Completion
You will be able to:
- Describe the features and functionality of the Hard IP for PCI Express block found in select Intel® FPGA devices
- Build a PCI Express solution targeting an FPGA using the Qsys system development tool
- Generate a testbench to simulate the Hard IP for PCI Express and modify the testbench to perform custom tests
- Debug a PCIe link using Intel FPGA debugging tools and transceiver features
- Some understanding of the PCI Express Protocol specification is helpful, but not required
- Familiarity with common high-speed transceiver architecture OR viewing the following: Transceiver Basics course OR attending the Building Gigabit Interfaces in Generation 10 or 28-nm Devices
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus design software
- Some familiarity with the Qsys design tool is helpful, but not required
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.