Getting Started with VHDL (Europe) (IEUVHDLSTART)

16 Hours Instructor-Led Only Course

Course Description

This 2-day class is an introduction to the VHDL language & its use in programmable logic design, covering constructs used in both the simulation & synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral & structural approaches. In the hands-on lab sessions, you will get to practice the knowledge you have gained by writing simple but practical designs. You will use VHDL constructs to parameterize your designs to increase their flexibility & reusability. You will also be introduced to testbenches, VHDL constructs used to build them, & common ways to write them. You will check your designs by compiling in the Quartus® II software v. 13.1 and simulating in the ModelSim®-Altera® tool.

At Course Completion

You will be able to:

  • Implement basic VHDL constructs
  • Use VHDL design units: entity, architecture, configuration, package
  • Create behavioral & structural models
  • Develop coding styles for efficient synthesis when:
  • Targeting device features
  • Inferring logic functions
  • Using arithmetic operators
  • Writing state machines
  • Use RTL Viewer to verify correct synthesis results
  • Incorporate Altera structural blocks
  • Write simple testbenches
  • Create parameterized designs

Skills Required

  • Background in digital logic design
  • Knowledge of simulation is a plus
  • Prior knowledge of a programming language (e.g., "C" language) is helpful, but not required
  • No prior knowledge of VHDL or Quartus II software is needed

Class Schedule

No class is being offered at this time.