During PPA configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera® device on the
DATA[7..0] pins. This configuration scheme is asynchronous, so control signals regulate the configuration cycle.
For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.
Using an intelligent host such as microprocessor or CPLD
MAX Series Configuration Controller Using Flash Memory white paper (PDF)
- Using a MAX® or MAX II CPLD as a configuration controller to configure Altera FPGAs from flash memory
- Source Code (ZIP) in Verilog and VHDL