Due to a problem in Intel® Quartus® Prime Pro software version 18.0 or earlier, when two partitions are compiled in two different projects with top_level_1.sv and top_level_2.sv, and are reused using the QDB_FILE_PARTITION assignment into a third project with top_level_3.sv you will see the following Internal Error because of overlapping row clock region:
Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_routing_constraints.cpp
The three top level files, top_level_1.sv, top_level_2.sv and top_level_3.sv are from 3 different designs and each design is different in terms of periphery interfaces, design blocks used etc. So, the developer project (projects with top_level_1.sv and top_level_2.sv) where the partitions are initially compiled and exported from does not have the overall information about the consumer project (project with top_level_3.sv) where the two exported partitions are reused.
- A clock sector defined by the green box in Figure. 1
- A row clock region is half-clock sector wide and one LAB row tall represented by the red dotted box in Figure. 1
- In consumer project when two reused partitions overlap in this region, you will see the above Internal Error