Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Tools

Last Modified: January 12, 2018
Version Found: v17.1 Update 1
Bug ID: FB: 515444;

Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen7_router_callbacks.cpp, Line: 349


Due to a problem in the Intel® Quartus® Prime Pro Edition software version 17.1 Update 1 and earlier, you may see this internal error during placement of a Intel® Stratix® 10 design containing multiple clock domains.

The internal error may occur when a design contains multiple asynchronous clock domains which have not been declared as being asynchronous in the Synopsys Design Constraints files (.sdc).


To work around this problem, ensure that all asynchronous clock domains are declared as being asynchronous using the set_clock_groups command.

For Example:
set_clock_groups -asynchronous -group [get_clocks <clock A>] -group [get_clocks <clock B>]


This problem is scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition software.