Type: Answers, Errata

Area: EMIF, Intellectual Property



Designs with Error Correction Coding (ECC) Do Not Work After Subsequent Reset

Description

Some designs with ALTMEMPHY-based DDR, DDR2, or DDR3 SDRAM high-performance controllers do not work with the Enable Error Detection and Correction Logic option turned on.

This issue affects all designs that use DDR, DDR2, or DDR3 SDRAM high-performance controllers with the Enable Error Detection and Correction Logic option turned on.

Your design does not work properly in both simulation and hardware after the subsequent reset.

Workaround/Fix

None.

This issue will be fixed in a future version.