ECC and CSR Designs May Fail in Simulation or Hardware

Designs created with the high-performance controller II (HPC II) version 11.0, and generated with the Enable Error Detection and Correction Logic or Enable Configuration and Status Register Interface options turned on can fail in simulation or in hardware.

The workaround for this issue is as follows:�

1. Open the <design_name>/submodules/alt_mem_ddrx_csr.v file in an editor.�
2. Make the following changes under Module Parameter Definition:� change BL_BUST_WIDTH = 4 to BL_BUST_WIDTH = 5� change MEM_IF_CSR_COL_WIDTH = 4 to MEM_IF_CSR_COL_WIDTH = 5� change MEM_IF_CSR_BANK_WIDTH = 2 to MEM_IF_CSR_BANK_WIDTH = 3� change MEM_IF_CSR_CS_WIDTH = 2 to MEM_IF_CSR_CS_WIDTH = 3�
3. At approximately line 1040, change the line: assign cfg_burst_length = csr_bl [BL_BUS_WIDTH - 1 : 0];� to� assign cfg_burst_length = {{(BL_BUS_WIDTH - 4){1’b0}}, csr_bl};

This issue will be fixed in a future version.