Type: Answers, Errata

Area: EMIF, Intellectual Property



Warning Messages Reporting Ignored SDC Constraints

Description

During compilation of a Qsys-generated IP core, the TimeQuest Timing Analyzer may display warning messages indicating that SDC constraints are being ignored. These messages appear because TimeQuest reads the altera_avalon_half_rate_bridge_constraints.sdc file even though the Half Rate Bridge feature is not used.

This issue affects all Qsys-generated configurations.

This issue has no design impact.

Workaround/Fix

To prevent display of the warning messages, remove the altera_avalon_half_rate_bridge_constraints.sdc file from the project and from any .qip file.

This issue will be fixed in a future version.