Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX

Type: Answers

Area: Intellectual Property

Last Modified: July 16, 2019
Version Found: v13.0 Service Pack 1
IP Product: PCI Express 1/2/4/8 Lanes (x8)
Bug ID: 2205809024

Why does my Cadence* NCSIM* Arria® V PCIe* simulation fail complete getting stuck in L0 and timeout?


Due to an issue when simulating the Arria® V Hard IP for PCI* Express* using Cadence* NCSim*  in Quartus® II version 13.0SP1 the simulation models must be updated.


The updated files can be found at and replace the existing files in location:

<your Quartus version>\quartus\eda\sim_lib\cadence

This problem has been fixed starting in Quartus® II version 14.0.