Device Family: Arria® II GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: Arria II GX FPGA Development Kit (RoHS) (2AGX125N)

Why is the PCI Express to DDR2 for Arria II GX Reference Design given by Altera not compiling successfully?

Description

The following error will appear during the fitter stage of compilation of pcie_ddr2_a2gx.zip design given on the link in Quartus® II software:

Error (176623): The source driving the following ports must be the same

Error (176624): Source top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_seq_wrapper:seq_wrapper|ddr2_sodimm_x64_phy_alt_mem_phy_seq:seq_inst|seq_mem_clk_disable drives port SRESET on atom top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_ddio

Error (176624): Source GND drives port SRESET on atom top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_clk_reset:clk|ddio_mimic

This issue exists in Quartus II software and IP version 10.1 and above.

Workaround/Fix

To resolve the error, you need to modify file ddr2_sodium_x64_phy_alt_mem_phy.v

Find "sreset" signal in module arriaii_ddio_in instantiation:

Change:

arriaii_ddio_in ddio_mimic(
    .datain     (fb_clk),
    .clk        (measure_clk_2x),
    .clkn       (),
    // synopsys translate_off
    .devclrn(),
    .devpor(),
   // synopsys translate_on
    .ena        (1\'b1),
    .areset     (1\'b0),
    .sreset     (1\'b0),
    .regoutlo   (),
    .regouthi   (mimic_data_2x),
    .dfflo      ()
);

To

arriaii_ddio_in ddio_mimic(
    .datain     (fb_clk),
    .clk        (measure_clk_2x),
    .clkn       (),
    // synopsys translate_off
    .devclrn(),
    .devpor(),
   // synopsys translate_on
    .ena        (1\'b1),
    .areset     (1\'b0),
    .sreset     (seq_clk_disable || ctrl_clk_disable[1]),
    .regoutlo   (),
    .regouthi   (mimic_data_2x),
    .dfflo      ()
);