An issue has been identified in multi-user environments with the UniPHY DDR3 SDRAM controller in Qsys. In an embedded system, this can result in error messages similar to the following:
- cpu: Nios II generation failed, input clock is unknown or set to 0
During generation, the Quartus® II software creates a directory "/tmp/compute_pll_temp" to hold temporary files regarding PLL calculations. However, this directory is not deleted on completion. The result is that if a different user then generates the core, permissions may prevent the PLL calculations being written.