Error (10170): Verilog HDL syntax error at <design>.v near text "localparam"; expecting "end", or an identifier ("localparam" is a reserved keyword ), or a sequential statement

This error occurs only in the Quartus® II software version 6.0 (including 6.0 SP1), if the design uses localparam declarations inside of generate statements, as in the example below, because the software enforces some Verilog language rules more strictly than all other versions.

generate
    for (i = 0; i < WIDTH; i = i 8)
    begin : my_loop
       localparam j = i 7 > WIDTH-1 ? WIDTH-1 : i 7;
       localparam k = BASE   (i>>3);

       ...
endgenerate

The Verilog language reference manual (LRM) states the following rule:

Module declarations and module items that shall not be permitted in a generate statement include: parameters, local parameters, input declarations, output declarations, inout declarations and specify blocks. 1364-2001 LRM 12.1.3

To avoid the error and implement the same functionality, put the local parameter statements inside an always block as in the example below:

generate

   for (i = 0; i < WIDTH; i = i 8)

   begin : my_loop

      always @(posedge clk or posedge reset)

         begin : my_params

            localparam j = i 7 > WIDTH-1 ? WIDTH-1 : i 7;

            localparam k = BASE   i>>3);

            ...

endgenerate