Device Family: Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Cyclone® V E, Cyclone® V GT, Cyclone® V GX, Cyclone® V SE, Cyclone® V ST, Cyclone® V SX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX
Type: Answers
Area: Component

Last Modified: August 31, 2015
Version Found: v11.0

Warning (205007): Truncated pin name <pin_name> in IBIS Output File to "IBIS pin name" to comply with IBIS 3.2/4.0/4.1 standard


Versions 4.1 and earlier of the IBIS specification restrict the length of the signal_name column to 20 characters or less.  When an FPGA deisgn has a top level port name that is longer than 20 characters, the Quartus® II software must truncate the name of the port to match the 20 character limit.


For Arria® V, Stratix® V and Cyclone® V devices, the Quartus II software supports generation of IBIS models to the more recent 4.2 and 5.0 versions of the IBIS specification which have an incerased 40 character limit on the signal_name column.

For Stratix V devices, the IBIS version may be selected by selecting the EDA Tool Settings: Board-Level category in the Settings dialog box available from the Assignments menu.

For Arria V and Cyclone V devices, the assignment must be added manually to the Quartus Settings (.qsf) file.
The assignment is:

set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION <version> -section_id eda_board_design_signal_integrity

Version may be set to 4P2 for version 4.2 support and 5P0 for version 5.0 support.


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