The Quartus® II software versions 2.1 and above include a Power-Up Don't Care logic option that causes registers to power up with a "don't care" logic level (X), or the logic level most appropriate for the design. This option is useful for allowing the Compiler to change the power-up level of a register to minimize the area of the design. When this type of optimization occurs, the compiler will issue the message above to warn you in case this behavior is undesired.
Previous versions of the Quartus II software did not have this option available. Therefore, in some cases where an older design was relying on the registers to power-up to a specific level, you may see differences in the way the design is synthesized. TTo revert to the power-up behavior of Quartus II software versions prior to 2.1, this option off using the Assignment Organizer in the Quartus II software versions 2.1 and 2.2 and the Assignment Ediotr in versions 3.0 and above.
An example of optimization that may occur with the Power-Up Don't Care option: A register may have its D input tied to VCC. If this option is turned off, the register powers up low (even though it will go high at the first clock signal). When this option is turned on, the compiler can set the power-up value of the register to high in this case and therefore has the option of optimizing the register away and setting the output of the register directly to VCC.
A specific case that might appear in your design could be an error signal that powers up low and is set high by some internal logic, which then feeds a DFF as described above. If the error signal goes high once, it will remain high. The Power-Up Don't Care option can assume that the register powers up high and remove the register, setting the output pin to a high value, which is not the desired behavior in this case.
To prevent this optimization, you can turn the Power-Up Don't Care option off. Alternatively, if you specify a clear signal in your HDL code, the Compiler can not remove the register even with the option on. It is good design practice to provide a clear or reset signal to any registers where your design relies on a specific power-up condition to operate correctly.
Another example of undesired optimization that may occur with the Power-Up Don't Care option: A case statement that implements a state machine might not have an explicit reset. There may also be states from which the state machine cannot escape. The Quartus II Compiler could assume that the state machine powers up in one of the stuck states and it can then optimize out the state machine logic in the design. The best solution is to follow the good design practice of resetting your state machines, and ensuring that you can escape from all states (if it is implemented as encoded rather than one-hot).