Device Family: Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

How do I connect my DDR3 controller to a 72-bit x4 DDR3 RDIMM?

Description

When designing a DDR3 controller with x4 DQS groups connected to a RDIMM, you must compare the DQ/DQS groupings of the controller to the DQ/DQS groupings in the RDIMM device specification.

For example, if the RDIMM is a Micron MT36JSF2G72PZ DIMM, the DQ/DQS groupings are different between the DDR3 controller and the functional diagram of the RDIMM. You must make sure that the DQS is grouped with the corresponding DQ bits, despite the name difference.

The DDR3 controller uses the following DQ/DQS mapping:
DQS0 - DQ3:0
DQS1 - DQ7:4
DQS2 - DQ11:8
...
DQS15 - DQ63:60
DQS16 - DQ67:64 (CB3:0)
DQS17 - DQ71:68 (CB7:4)

The 72-bit RDIMM uses the following DQ/DQS mapping:
DQS0 - DQ3:0
DQS1 - DQ11:8
DQS2 - DQ19:16
...
DQS15 - DQ55:52
DQS16 - DQ63:60
DQS17 - CB7:4 (DQ71:68)

You cannot change the mapping of the DDR3 controller. The DQ pins on the FPGA can connect directly to the pins on the RDIMM connector with the same names. DQS0 and DQS17 match between the two, but DQS1 thru DQS16 need to be remapped on the board. The mapping should be as follows:

FPGA pin connects to RDIMM Connector pin
---------------------------------------------------------
DQS0                         DQS0
DQS1                         DQS9
DQS2                         DQS1
DQS3                         DQS10
DQS4                         DQS2
DQS5                         DQS11
DQS6                         DQS3
DQS7                         DQS12
DQS8                         DQS4
DQS9                         DQS13
DQS10                       DQS5
DQS11                       DQS14
DQS12                       DQS6
DQS13                       DQS15
DQS14                       DQS7
DQS15                       DQS16
DQS16                       DQS8
DQS17                       DQS17

With this mapping, the DQ bits are grouped with the corresponding DQS bits on the FPGA and on the RDIMM. The design should compile successfully in the Quartus® II software and calibrate successfully on the board.