Device Family: Intel® Arria® 10

Device Family: Arria® V

Device Family: Cyclone® V

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Intel® Stratix® 10

Device Family: Intel® Stratix® 10 GX

Device Family: Intel® Stratix® 10 SX

Device Family: Stratix® V

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: Component

What bandwidth settings does Altera recommend when cascading PLLs?


When cascading PLLs in Altera® FPGAs, the best practice is to use a low bandwidth setting for the first PLL and a high bandwidth setting for the downstream PLL. 

The first PLL acts as a jitter filter when configured as low bandwidth and there is very little jitter transferred to the downstream PLL.  Using a high bandwidth setting on the downstream PLL allows it to track jitter from the first PLL.  Ensure there is no overlap of the bandwidth ranges of the two PLLs.  The bandwidth ranges for each PLL parameterization in your design project is shown in the Quartus® II software compilation report.

Refer to the respective device family handbook to see if PLL cascading is supported as well as PLL Clock Management Features in Altera FPGAs.