Article ID: 000077960 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Why does the ATX PLL REFCLK switching not work in simulation when using the Stratix V GX Custom or Low Latency PHY in Quartus II Software version 12.0?

Environment

  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the simulation model, the ATX PLL REFCLK switching does not work when using the Stratix® V GX Custom or Low Latency PHY in Quartus® II Software version 12.0.

    Resolution

    To work around this issue, you can temporarily select the CMU PLL in the PHY MegaWizard™ to simulate REFCLK switching.

    This issue will be fixed in a future version of Quartus.

    Related Products

    This article applies to 2 products

    Stratix® V GX FPGA
    Stratix® V FPGAs

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