Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller supporting ALTMEMPHY

Are there any known issues with the Registered DIMM (RDIMM) variant of DDR3 High Performance Controller IP in Quartus II software versions 9.1SP1 and SP2?

Description

Yes, In Quartus® II software and IP versions 9.1SP1 and 9.1SP2 the DDR3 RDIMM configuration bit stream is programmed into the RDIMM module in the reverse order. To work around this problem please reverse bitstream in the RDIMM_CONFIG_BITS parameter in the generated HDL files by editing the following sections:

nIn file <var>_phy_alt_mem_phy_seq_wrapper.v
-Line: “localparam RDIMM_CONFIG_BITS = …”
n
 
and
 
In file <var>_phy.v
-
Line: <var>phy_alt_mem_phy_inst.RDIMM_CONFIG_BITS = …”
 
for example if RDIMM_CONFIG_BITS = "0000000010101101000000000000000000000000000000000000000000000000"
 
it will need to be chnaged to RDIMM_CONFIG_BITS =
"0000000000000000000000000000000000000000000000001011010100000000"
 
This will be fixed in the future version of Quartus II software.