Follow these instructions to program the dynamic I/O delay chains using the ALTIOBUF megafunction in Stratix® V, Arria® V, and Cyclone® V devices.
Each IOE programmable delay transaction requires 40 clock cycles with io_config_clkena asserted. The LSB should be your first bit (io_config_datain) at the beginning of your transaction. You can find the bit format information for each device family in the ALTDQ_DQS2 Megafunction User Guide (PDF). Use table 4-1 for Stratix V devices, table 4-3 for Arria V, and Cyclone V devices. Each IOE programmable delay is 6 bits wide. The reserved bits should be set to zero. The io_config_update should be asserted after the 40th clock cycle.