Dynamic On Die Termination (ODT)
Dynamic ODT is a new feature on DDR3 SDRAM memories and not available in DDR2 SDRAM memories.
Dynamic ODT provides systems with increased flexibility to optimize termination values for different loading conditions e.g. Multi Rank design
For optimum signaling, a typical dual-slot system will have a module terminate to a low impedance value (30. or 40.) when in an idle condition.
When the module is being accessed during a write operation, greater termination impedance is desired, for example, 60. or 120..
Dynamic ODT enables the DRAM to switch between high or low termination impedance without issuing a mode register set command.
Dynamic On-Chip Termination (OCT)
Dynamic On-Chip Termination (OCT) is a feature on Stratix® III and Stratix IV FPGA devices.
Dynamic OCT provides on chip termination to DDR3 SDRAM interface pins on the FPGA side removing the need for on board termination hence saving board space.
One dynamic OCT control is available per DQ/DQS group. Stratix III and Stratix IV devices support on and off dynamic termination switching between series and parallel termination for a bidirectional I/O in all I/O banks.
· Dynamic parallel termination
- Is enabled only when the bidirectional I/O acts as a receiver and
- Is disabled when it acts as a driver.
· Dynamic series termination
- Is enabled only when the bidirectional I/O acts as a driver and
- Is disabled when it acts as a receiver.
This feature is useful for terminating any high-performance bidirectional path because signal integrity is optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead of external. Also, termination only switches on during input operation, thus drawing less static power.