Device Family: Arria® II GX, Stratix® III, Stratix® IV E, Stratix® IV GT, Stratix® IV GX, Stratix® V E, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why does avl_ready deassert after avl_write_req is asserted in my DDR3 and DDR2 SDRAM High Performance Controller II IP?


When ECC is enabled, you will see avl_ready de-assert after avl_write_req is asserted increasing the Write latency. It is because the controller needs to wait for incoming data (deassert ready signal) and then decide if read-modify-write operation is required during command loading.


This behavior will not occur if ECC is disabled.

This issue will be fixed in a future version of the Quartus® II software.