Device Family: Stratix® V E, Stratix® V GT, Stratix® V GX

Type: Answers

Area: EMIF, Intellectual Property

IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 2.5V.


This error might happen if you are trying to implement DDR3L SDRAM interface using UniPHY based controller IP. DDR3L SDRAM interface uses SSTL-1.35V I/O standard, the oct_rzq pin also requires the SSTL-1.35V I/O standard.


Make the following assignment manually in your project QSF file:

set_instance_assignment -name IO_STANDARD "SSTL-135" -to oct_rzqin