Introduction
If your DDR3 SDRAM Controller with UniPHY design at 533MHz meets the basic criteria listed below and you have performed some preliminary analysis of a compiled design instantiated with your desired memory interface configuration, you should notify your local FAE and request further communication with the HardCopy Technical Marketing team and the HardCopy Design Center (HCDC) about the design opportunity.The HCDC will request further analysis of the design and potentially need to perform a trial place and route of the design in the HCDC ASIC design flow to confirm timing closure is achievable on the given design before any acceptance of the design for HardCopy migration (DR2 milestone) will take place.
Background
The Quartus® II software version 10.1of the UniPHY DDR3 Megafunction has been validated by the HardCopy Design Center through trial route, though no physical tape-out of the test design was done.
The design was done using Quartus II software version 10.1 Build 145, and was constructed using a single memory controller interface configured for a single-rank 72-bit wide (DQ) DDR3 533 MHz interface all contained on one edge of the device I/O, using the HC4GX35FF1152 at Commercial operating conditions (0C and 85C Junction Temperature). Timing closure was achieved for the given test case across all PVT corners analyzed, but with very little positive slack remaining (<20ps positive setup margin). Because the margin is very limited, it is quite possible that some implementations built using an FPGA prototype could work for the FPGA in system testing, but may have problems if migrated to a HardCopy® device and is not shown to completely meet all timing requirements in static timing analysis. There are inherent physical differences and implementation differences between the FPGA and HardCopy devices that prevent the timing results from ever being identical between the two devices.
The design setup used the default board and slew rate parameters provided in the UniPHY Megafunction as shown in the dut_timing.tcl file generated by the IP Megawizard.
Because every designed system is unique, it is important for you to compare these settings with your system environment to see if your design is comparable to these settings or not. Some implementation details will vary and can either help or hinder the timing slack results. For example, worsening slew rates on I/O will harm DQ/DQS write capture timing margin, but tighter board trace skew within a DQ/DQS group would help timing margin.
Design Criteria
Basic requirements for HardCopy IV GX designs using 533 MHz DDR3 SDRAM Controller with UniPHY:
· Only use the DDR3 UniPHY IP released with Quartus II software version 10.1 or later. The Altmemphy IP will not achieve 533 MHz in Hardcopy IV GX devices.
· Use HardCopy IV GX devices with FF package only, LF or WF packages will not achieve 533 MHz; Your FPGA companion choices are open depending upon your density needs.
· Single rank implementation is supported, multi-rank implementations will have reduced performance limits and will not achieve 533 MHz due to the increased parasitic loading per pin on the HardCopy and FPGA devices and limitations in deskew.
· Commercial operating conditions should be specified in the project setup (0C and 85C for min/max junction temperature). Hardcopy IV GX devices will not achieve timing closure for a 533 MHz DDR3 interface for Industrial operating conditions.
· I/O wraparound is not guaranteed to work for DDR3 at 533 MHz in Hardcopy IV GX devices. Contain the entire DDR3 memory interface I/O locations on the same edge of the die using the Pin Planner and I/O bank information. All address and command pins as well as DQ/DQS/DM pins as well as the reference clock input for the PLL used in the DDR3 Megafunction.
· Do not drive the reference clock to the PLL through an internal path prior to the PLL reference inclk pin. This includes a reference clock entering on different edge I/O pin and routing via a Global Clock resource to where the DDR3 IP instantiated PLL location resides. Use a primary clock input pin adjacent to the PLL location to provide your reference clock to the PLL. Do not cascade PLL reference clocks.
· Conform as best as possible to the default timing and board trace delay settings found in the DDR3 IP Megawizard when building your memory interface design. Any deviation beyond the values specified may prevent successful timing closure of the memory interface.
· Design to have shared control of and synchronize the reset signals of the DDR3 IP controller and data path logic. Design such that it can asynchronously assert the reset to all areas, but synchronously remove the reset within the local clock domains to ensure proper reset recovery and removal.
· Use simulation tools to extract worst case slew rate data on memory I/O interfaces and provide that information in the DDR3 IP Megawizard to improve timing accuracy and timing margin. If simulation tools are not available, use the Advanced I/O Timing (AIOT) Board Model Planner found in Quartus II software Pin Planner to model your board trace environment and upon compilation of the design, extract the worst case reported slew rate data from the TimeQuest STA report from the “Signal Integrity Metrics” section of the <revision>.sta.rpt file. Use that slew rate information in place of simulation derived data in the DDR3 IP Megawizard, then remove the AIOT board modeling from your design for the DDR I/O interface pins so the board parasitic is not double counted in analysis, as the DDR3 IP megawizard timing constraints and calibration analysis will account for the board effects if the parameters are entered in the Megawizard correctly.
· Build user accessible control into your design for the debug interface ports and DLL/PLL reconfiguration ports available in the DDR3 IP Megawizard when the “HardCopy compatibility” checkbox is enabled in the Megawizard setup.