Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR3 SDRAM Controller MegaCore supporting UniPHY

Why do I see errors when compiling Qsys system for DDR3 UniPHY based controller with Hard Processor System (HPS)?

Description

You may see the following errors during the Analysis & Synthesis compilation stage for DDR3 UniPHY based controllers using Qsys for HPS system:

Error: Input port DATAIN on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port DATAIN is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal


Error: Input port ENA on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port ENA is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal


Error: Input port UPDATE on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured
    Info (129003): Input port UPDATE is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal

Workaround/Fix

This issue is caused by using deferred generation of the Qsys system, where the DDR3 controller is generated on the fly during compilation. The correct method to properly compile the design is as follows:

1) Create the Qsys system
2) In the Qsys system, generate the DDR3 controller IP
3) Include the resulting .qip file into your project files and not the .qsys file.