Device Family: Arria® II GX

Device Family: Arria® II GZ

Device Family: Arria® V GT

Device Family: Arria® V GX

Device Family: Arria® V GZ

Device Family: Arria® V ST

Device Family: Arria® V SX

Device Family: Cyclone® IV E

Device Family: Cyclone® IV GX

Device Family: Cyclone® V E

Device Family: Cyclone® V GT

Device Family: Cyclone® V GX

Device Family: Cyclone® V SE

Device Family: Cyclone® V ST

Device Family: Cyclone® V SX

Device Family: Stratix® III

Device Family: Stratix® IV E

Device Family: Stratix® IV GT

Device Family: Stratix® IV GX

Device Family: Stratix® V E

Device Family: Stratix® V GS

Device Family: Stratix® V GT

Device Family: Stratix® V GX

Type: Answers

Area: EMIF

Area: Intellectual Property


IP Product: DDR2 SDRAM Controller supporting ALTMEMPHY

How do I implement the half rate bridge option for connection to a full rate memory controller ?

Description

While using the Quartus® II software  versions before 11.0, the half rate bridge option was a selectable parameter in the memory controller IP megawizard.

While using the Quartus II software versions 11.0 and later, the only Altera IP supported option for the half rate bridge is to use the SOPC Builder Avalon-MM DDR Memory Half-Rate Bridge component. This can be used in a QSYS project in the latest release of the Quartus II software.

For documentation on a half rate bridge, see the Avalon Memory Mapped Bridges chapter of the SOPC Builder User Guide.