Incorrect Register Value After Tx/Rx Reset

To overcome this issue, write or read the following addresses to clear the registers as shown in table below.

Registers

Workaround

0x0FE-0x0FF: Tx Underflow Truncated Data Frame Count

After tx_rst_n, read at address 0x03E to clear the register.

0x0FC-0x0FD: Rx Overflow Truncated Packet Count

After rx_rst_n, read at address 0x0FC to clear the register.

0x0FE-0x0FF: Rx Overflow Dropped Packet Count

After rx_rst_n, read at address 0x0FE to clear the register.

0x140-0x17E: Tx Statistics

After tx_rst_n, write 0x1 to address 0x140 to clear the statistics counter.

0x1C0-0x1FE: Rx Statistics

After rx_rst_n, write 0x1 to address 0x1C0 to clear the statistics counter.

0x240: ECC Error Status

After tx_rst_n or rx_rst_n, read at address 0x240 to clear the registers.

This issue will be fixed in a future version of the Low Latency 10GbE MAC MegaCore function.