Article ID: 000076487 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP-generated MATLAB* model and the HDL model?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • FFT Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the FFT Intel® FPGA IP version 19.1, you may observe the above problem in the simulation if the Data Output Width of the IP is not configured to the maximum supported width. 

    Resolution

    To work around this problem configure the Data Output Width to the maximum supported width in IP.

    This problem is currently not scheduled to be fixed in a future version of the FFT Intel® FPGA IP.

    Related Products

    This article applies to 10 products

    Arria® V FPGAs and SoC FPGAs
    Stratix® IV FPGAs
    Arria® II FPGAs
    Intel® MAX® 10 FPGAs
    Cyclone® IV FPGAs
    Stratix® V FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs

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