Device Family: Intel® Arria® 10, Arria® II, Arria® V, Intel® Cyclone® 10, Cyclone® IV, Cyclone® V, Intel® MAX® 10, Intel® Stratix® 10, Stratix® IV, Stratix® V

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: DSP, Intellectual Property

Last Modified: July 15, 2020
Version Found: v19.1
Bug ID: 1508145050

Why is there a mismatch in the FFT Intel® FPGA IP output result in simulation between the IP generated MATLAB* model and the HDL model?


Due to a problem with the FFT Intel® FPGA IP version 19.1, you may observe the above problem in simulation if the Data Output Width of the IP is not configured to the maximum supported width. 


To work around this problem configure the Data Output Width to the maximum supported width in IP.

This problem is currently not scheduled to be fixed in a future version of the FFT Intel® FPGA IP.