Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: November 04, 2020
Version Found: v19.3
Bug ID: 14010045894
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does my Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* End Point show lower read performance with the Intel® Quartus® Prime Pro version 19.3?

Description

The Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* supports up to 64 outstanding requests with a Max Read request size of 512 Bytes with the Intel® Quartus® Prime Pro version 19.3. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput. 

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.