Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.2 and earlier, you may see this error when trying to generate the example design for the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* with “Enable HIP dynamic reconfiguration of PCIe registers” feature enable.
Device Family: Intel® Agilex™ Series, Intel® Stratix® 10 DX
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: August 18, 2020
Version Found: v20.2
Bug ID: 14011282290
IP: pci-express, Avalon-MM Stratix 10 Hard IP for PCI Express