Due to the wrong reference code from UG-01145_avst 2017.05.15 - 6.12.1 for Configuration Space Register Access Timing, the Intel® Arria® 10 and Intel® Cyclone® 10 PCIe* Transaction Layer Configuration Space access will not be stable. This is because the tl_cfg_* interface are covered by multi-cycle constraints, but the code doesn't match it.
The code is as following:
always @(posedge coreclkout_hip)
begin
// detect address change
cfg_addr_reg[3:0] <= tl_cfg_add[3:0];
cfgctl_addr_change <= cfg_addr_reg[3:0] != tl_cfg_add[3:0];
...
end
To work around this problem, upgrade the reference code as UG-01145_avst | 2019.05.22 - 5.12.1 for Configuration Space Register Access Timing.
One more pipeline is added to avoid multi-cycle timing risk.
The code is as following:
always @(posedge coreclkout_hip)
begin
tl_cfg_add_reg <= tl_cfg_add[0];
tl_cfg_add_reg2 <= tl_cfg_add_reg;
end
// detect the address change to generate a strobe to sample the input32-bit data
always @(posedge coreclkout_hip)
begin
cfgctl_addr_change <= tl_cfg_add_reg2 != tl_cfg_add_reg;
cfgctl_addr_change2 <= cfgctl_addr_change;
cfgctl_addr_strobe <= cfgctl_addr_change2;
end