Article ID: 000080673 Content Type: Troubleshooting Last Reviewed: 09/10/2019

Why does programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel® FPGA IP is in ILAS phase bring the IP back to CGS state?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • JESD204B Intel® FPGA IP
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    Description

    Due to a known problem in the Intel® Quartus® Prime Standard and Pro Edition Software, programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel FPGA IP is in ILAS phase will bring the IP back to CGS state. This impacts Intel Agilex®, Intel Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX device families.

    Resolution

    To work around this problem, avoid programming the csr_cgs_bypass_sysref register bit when the JESD204B Intel FPGA IP is in ILAS phase. There is no fix planned for this. 

    Related Products

    This article applies to 4 products

    Intel® Cyclone® 10 GX FPGA
    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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