Device Family: Intel® Agilex™, Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: Intellectual Property


Last Modified: September 10, 2019
Version Found: v18.1
Bug ID: 1507197255
IP: JESD204B

Why does programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel® FPGA IP is in ILAS phase bring the IP back to CGS state?

Description

Due to a known problem in the Intel® Quartus® Prime Standard and Pro Edition Software, programming the csr_cgs_bypass_sysref register bit to '0' when the JESD204B Intel FPGA IP is in ILAS phase will bring the IP back to CGS state. This impacts Intel Agilex®, Intel Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX device families.

Workaround/Fix

To work around this problem, avoid programming the csr_cgs_bypass_sysref register bit when the JESD204B Intel FPGA IP is in ILAS phase. There is no fix planned for this.