Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: October 23, 2019
Version Found: v19.1
Bug ID: 14010223298
Document ID: UG-20032, UG-20033
IP: Avalon-MM Stratix 10 Hard IP for PCI Express, Avalon-ST Stratix 10 Hard IP for PCI Express

Does the Intel® Stratix® 10 PCIe* Hard IP support Root Port Mode Type 0 TLP Configuration Requests?

Description

The Intel® Arria® 10 PCIe* Hard IP (HIP) supports the Root Port Mode Configuration Requests in which Configuration Type 0 TLPs can be sent into the HIP via the Avalon®-ST TX interface to read/write the HIP's local Configuration Space when it's operating in Root Port mode.

However, Type 0 Root Port Mode Configuration Requests capability is NOT supported in the Intel® Stratix® 10 PCIe* HIP operating in Root Port mode. The user is directed to use the HIP Reconfiguration interface to access the local Configuration Space.

Workaround/Fix

 

The Intel® Stratix® 10 PCIe* Hard IP user guides will be updated to explicitly state that Type 0 Root Port Mode Configuration Requests capability is not supported.