Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX

Type: Answers

Area: Intellectual Property


Last Modified: May 13, 2019
Version Found: v18.1 Update 2
Bug ID: 1707015093

Does the Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP support changing the BAR size at run-time before enumeration?

Description

The Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP does not support changing the BAR size at run-time before enumeration. The BAR Size Mask can only be set during IP GUI configuration and HDL generation.

Workaround/Fix

Not applicable.