Device Family: Intel® Stratix® 10

Type: Errata

Area: Intellectual Property


Last Modified: May 29, 2018
Version Found: v18.0
Bug ID: FB: 553657;

Why does the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design fail timing in Stratix 10 ES1 device?

Description

Due to a problem in Intel® Quartus® Prime version 18.0, the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design may fail timing closure. 

Workaround/Fix

Launch Design Space Explorer II and perform seed sweep to get best quality of fitter placement as Stratix® 10 FPGA timing model is still at preliminary stage pending engineering characterization.