Article ID: 000082826 Content Type: Troubleshooting Last Reviewed: 02/14/2023

Why does the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design fail timing in Intel® Stratix® 10 ES1 device?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem in Intel® Quartus® Prime Software version 18.0, the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design may fail timing closure. 

     

     

    Resolution

    Launch Design Space Explorer II and perform seed sweep to get best quality of fitter placement as Stratix® 10 FPGA timing model is still at preliminary stage pending engineering characterization.  

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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